An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination
نویسندگان
چکیده
منابع مشابه
High-Throughput and Memory Efficient LDPC Decoder Architecture
Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. The decoder implementation complexity has been the bottleneck of its application. This paper presents a new kind of high-throughput and memory efficient LDPC decoder architecture. In general, more than fifty percent of memory can be saved over conven...
متن کاملArchitecture of a low-complexity non-binary LDPC decoder for high order fields
In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC codes, presented in [10]. To the knowledge of the authors this is the first implementation of a GF(q) LDPC decoder for high order fields (q ≥ 64). The originality of the proposed architecture is that it takes into account the memory problem of the nonbinary LDPC decoders, together with a signif...
متن کاملAn Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture
This paper presents an area-efficient halfrow pipelined layered low-density parity check (LDPC) decoder architecture for IEEE 802.11ad applications. The proposed decoder achieves a good tradeoff between throughput and area because of its ability to overcome the low-throughput bottleneck in conventional half-row decoders and the highcomplexity bottleneck in fully parallel decoders. Synthesis res...
متن کاملAn Efficient LDPC Decoder Architecture with a High-Performance Decoding Algorithm
In this work, a high performance LDPC decoder architecture is presented. It is a partially-parallel architecture for low-complexity consideration. In order to eliminate the idling time and hardware complexity in conventional partially-parallel decoders, the decoding process, decoder architecture and memory structure are optimized. Particularly, the parity-check matrix is optimally partitioned i...
متن کاملEnergy-Efficient LDPC Decoder using DVFS for binary sources
This paper deals with reduction of the transmission power usage in the wireless sensor networks. A system with FEC can provide an objective reliability using less power than a system without FEC. We propose to study LDPC codes to provide reliable communication while saving power in the sensor networks. As shown later, LDPC codes are more energy efficient than those that use BCH codes. Another m...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IEEE Access
سال: 2019
ISSN: 2169-3536
DOI: 10.1109/access.2019.2896012